Cycle
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Operations
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Load Address
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SR to X; X to Z; Z to PC
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Deposit
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PC to A and MA; SR to X; X to Z and Write Data; Mem Write; Z to MB; Inc PC
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Examine
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PC to A and MA; Read Data to Y; Y to Z; Z to MB
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Fetch
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PC to A; Read Data to IR and Y; Y to Z; Z to MB; EA to MA; Inc PC
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Defer
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MA to A; Read Data to Y; if auto-index then {Y+1 to Write Data and Z; Mem Write} else {Y to Z}; Z to MA
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Execute
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AND
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MA to A; AC to X; Read Data to Y; X AND Y to Z; Z to AC
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TAD
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MA to A; AC to X; Read Data to Y; X + Y to Z; Z to AC; L XOR Carry Out to L
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ISZ
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MA to A; Read Data to Y; Y + 1 to Write Data; Mem Write; if result = 0 then {Inc PC}
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DCA
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MA to A; AC to X; X to Write Data; Mem Write; 0 to AC
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JMP
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MA to Y; Y to Z; Z to PC
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JMS
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MA to A; PC to Y and Mem Data; Mem Write; Y + 1 to Z; Z to PC
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IOT
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AC to X; other operations as determined by I/O device
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IAC
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AC to X; X + 1 to Z; Z to AC
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RAL
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AC to X; <L, X> rotated left 1 to <L, Z>; Z to AC
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RTL
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AC to X; <L, X> rotated left 2 to <L, Z>; Z to AC |
RAR
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AC to X; <L, X> rotated right 1 to <L, Z>; Z to AC |
RTR
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AC to X; <L, X> rotated right 2 to <L, Z>; Z to AC |
CML
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L XOR 1 to L
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CMA
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AC to X; ~X to Z; Z to AC
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CIA
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AC to X; ~X + 1 to Z; Z to AC |
CLL
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0 to L
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STL
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1 to L
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CLA
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Z to AC
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STA
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ones to Y; Y to Z; Z to AC |
OSR
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AC to X; X to Z; SR to Z; Z to AC
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Skip
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If skip condition then {IncPC}
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