Gating Signal Conditions

The following logical equations define the conditions under which each data path gating signal is asserted.

Signal
Condition
PC2A
DEPOSIT + EXAMINE + FETCH
MA2A
DEFER + AND + TAD + ISZ + DCA + JMS
MEM2Y
EXAMINE + FETCH + DEFER + AND + TAD + ISZ
PC2Y
JMS
MA2Y
JMP
AC2X
AND + TAD + IOT + IAC + ROT + CMA + OSR + DCA
PC2MA
DEPOSIT + EXAMINE
EA2MA
FETCH
Z2MA
DEFER
SR2Z
LDADR + DEPOSIT + OSR
IO2Z
IOT
LDIR
FETCH
LDPC
LDADR + JMP + JMS
INCPC
DEPOSIT + EXAMINE + FETCH + ISZ . ZERO + SKIP*
LDMA
DEFER + FETCH + DEPOSIT + EXAMINE
LDMB
DEPOSIT + EXAMINE + FETCH + ISZ
LDAC
AND + TAD + DCA + IAC + ROT + CMA + CLA + OSR
LDL
TAD + CML + CLL
CIN
AUTOIND + ISZ + IAC + JMS
RNONE
LDADR + DEPOSIT + EXAMINE + FETCH + DEFER + TAD + DCA + JMP + JMS + OPR . /ROT
PC2MEM
JMS
ALU2MEM
DEPOSIT + DEFER + ISZ + DCA
MEMWR
DEPOSIT + AUTOIND + ISZ + DCA + JMS

Auxiliary Terms

Signal
Condition
AUTOIND
DEFER . (A Bus value in range 010-017)
ROT
RAL + RTL + RAR + RTR
ZERO
ALU output = 0