BREDSAC Design - Preliminary Thoughts
Technology Level
I want to make use of parts from my junk box wherever possible, which
means largely using 74 series TTL and parts from a similar era. Any new
parts that I buy will probably be 74HC, as TTL is becoming hard to get
these days.
There will be no microcontrollers or other ready-made programmable parts -- that would be cheating.
Serial or Parallel?
In keeping with the spirit of the original, and to keep the part count
down to something reasonable, BREDSAC will be a serial machine. While
this means it won't be blazingly fast, it will still probably be quite
a lot faster than the original -- more on that later.
Memory
For the memory, I intend to use a pair of 16k x 1 bit dynamic RAM chips
(4116 or equivalent). Why dynamic rather than static? Various reasons.
Serial operation means that a 1-bit wide RAM makes the most sense, and
the only sufficiently large 1-bit memory chips I have lying around
happen to be dynamic. It provides an excuse for the word BREDSAC to
have a D in it. The EDSAC used mercury delay lines for its memory,
which also needed continuous refreshing, so it's kind of authentic. And
apparently I don't like to make things too easy for myself. :-(
The use of dynamic memory will have a side benefit. As a by-product of
the refresh process I should be able to derive a signal that I can send
to an oscilloscope to produce something very like the original EDSAC's
CRT memory display.
Registers
There are a couple of ways I could go about implementing the registers.
The most obvious would be to use shift registers. This would be the
most similar to the way the original machine operated, and if I use
serial-in parallel-out types it would be very easy to display the
contents of the registers by connecting LEDs to the outputs. However,
it would require a lot of parts -- 71 bits for the accumulator plus
another couple of 17-bit registers would add up to about 15 or so chips.
Another possibility would be to use RAMs. I have some 1k by 1 bit
static RAM chips, one of which would be enough to hold all the required
data, although I would probably use two or three to allow for
simultaneous access to multiple registers. The disadvantage is that it
wouldn't be so easy to display register contents, but should be
possible to generate an oscilloscope display of the memory holding the
registers much the same way as with the main memory. This would also be
very authentic-looking.
For now I'm going with the static RAM design, although I might change my mind later.
Bootstrapping
I actually have a few genuine uniselectors, but nowhere near enough of
them to recreate the original EDAC's method of loading the initial
orders. Unless I come up with some other hare-brained scheme, I'll
probably be using an EEPROM.
I/O Devices
I have a real 5-bit teleprinter, although it uses a completely
different character encoding from the original EDSAC, so some kind of
translation would be needed in between. It's also extremely noisy, so
while I might try to get it working as a proof of concept, I will
probably arrange something else as an alternative, such as maybe a DEC
VT52 or a Commodore 64 (both of which I also happen to have... yes, I
have far too much junk.)
I don't have any paper tape equipment, though, and the prospects of
acquiring any at any kind of realistic cost appear very slim, so I plan
to build an optical tape reader, and prepare tapes for it by a process
involving a relatively modern computer, a laser printer, a guillotine
and some sticky tape.
On the plus side, I have a genuine telephone dial of about the right
vintage that there shouldn't be any problems incorporating. It will
doubtlessly be the most authentic part of the whole project.