More Jump Instructions
I found while writing the test program that programming with just the
two original EDSAC jump instructions was quite awkward, so I added a
couple of instructions from a later version of the machine: an
unconditional jump, and a jump if AC nonzero.
To support the jump if nonzero instruction, I connected my one
remaining ubranch multiplexer input to the zero FF output from the ALU.
(I hope I won't need any more ubranch conditions!)
Both of the new jump instructions are encoded with opcode F, and
distinguished by instruction bit 0. Accordingly, they are written in
assembly language as
F addr F # Jump
F addr D # Jump if nonzero
(In the original version of the EDSAC, opcode F was "Read the last
character output for verification". I don't think I will miss that.)
New ubranch input:
Microcode for the new jump instructions:
# UBCOND values
BNZER = 111 # Zero FF = 0
# F F - Unconditional jump
10001 0 0001 : - EOI 11 X0 - Y0 CY0 -- - - MSW LSW - - - JUMP - BSGN0 ----
# F D - Jump if accumulator <> 0
10001 1 0001 : - - 00 XAC - Y0 CY0 -- - - - LSW - - - --- - --- ----
10001 1 0010 : - - 10 XAC - Y0 CY0 -- - - - - - - - --- - --- ----
10001 1 0011 : - - 01 XAC - Y0 CY0 -- - - - - - - - --- - --- ----
10001 1 0100 : - EOI 11 XAC - Y0 CY0 -- - - MSW - - - - JUMP - BNZER ----
Fixing Bit 17
While testing the Jump if Nonzero instruction, I found a problem.
The ALU, and also the right-shifting mechanism, works on full 18-bit
words with the sign bit in bit 17. It needs to be this way, because a
one-bit overflow of intermediate results during multiplication has to
be accommodated. As long as the final results of arithmetic operations
don't overflow, bits 16 and 17 should be the same, but there are ways
for them to become different, which can lead to the Zero FF being set
incorrectly.
To fix this, I did two things:
1. In the ALU, the Zero FF is not updated during bit 17.
2. Bit 17 is forced to be the same as bit 16 when reading an operand
from memory. This is done by a transparent latch after the output of
the RAM that is frozen during bit 17 of an MSW. (A separate output is taken
directly from the RAM for display refresh, so that the actual memory
contents can be seen).
Two new timing signals are derived for these purposes, TVAL (Valid Bit) and TCPUVRD (Valid Bit during CPU Read cycle).
New ALU subcircuit:
New main memory subcircuit:
